(1) Field of the Invention
The present invention relates to an information processor that has an operation flag register reflects the result of an operation in an instruction by updating operation flags.
(2) Description of the Related Art
Recently, information processors, for instance, microcomputers, have been drastically developed and used in a variety of fields.
Generally speaking, an information processor increases the throughput by executing a plurality of instructions in such as the VLIW (Very Long Instruction Word) and the superscalar method in parallel.
A conventional information processor includes a flag register for storing operation flags, for instance, a carry flag or an overflow flag. When executing an arithmetical instruction, the conventional information processor creates operation flags and updates the flag register. The conventional information processor refers to an operation flag that is the condition in a conditional branch instruction. As a result, the compiler or the assembler for the information processor has to schedule the instructions in a program so that an arithmetical instruction that changes the operation flags is not executed between an arithmetical instruction and a conditional branch instruction.
It is pretty much difficult for the compiler or the assembler to schedule such instructions for a processor that executes instructions in parallel in order to increase the throughput (for instance, a VLIW processor).
An information processor for which a compiler may schedule instructions easily without changing operation flags has developed. Such an information processor includes a plurality of operation flag registers, and each of the instructions designates a flag register that is to be updated (refer to, for instance, "PowerPC601 User's Manual, IBM Microelectronics").
FIGS. 1A and 1B show the specification of arithmetical instructions of the conventional information processor and the construction of the operation flag registers.
The information processor includes two flag registers, that is, flag register CR (Condition Register) and flag register XER (Integer Exception Register) shown in FIG. 1B. The flags are set in these registers as shown in FIG. 1B.
For the information processor, four different arithmetical instructions that perform the same arithmetical operation are prepared (FIG. 1A shows only add instructions).
FIG. 1A shows when a period "." is added to the mnemonic ("add"), the operation flag in flag register CR is updated, and when the alphabet "o" is added to the mnemonic, the operation flag in flag register XER is updated.
For one add instruction, four kinds of instruction are prepared. The instruction to update no flag register, the instruction to update flag register CR, the instruction to update flag register XER, and the instruction to update flag register CR and flag register XER are prepared.
It is easy for the compiler or the assembler to schedule instructions using such instructions. For instance, it is easy to arrange an arithmetical instruction to update no flag register between an arithmetical instruction to update flag register CR and a conditional branch instruction.
According to the conventional art, however, the length of an instruction code and the code size are increased since one of four instruction codes (op (operation) codes) has to be assigned to an instruction depending on which flag register should be updated.
For instance, an instruction code for a "PowerPC601" processor is lengthy. This is because one bit of field showing whether a period "." is included and another one bit of field showing whether the alphabet "o" is included are set in almost all such instruction codes.
A plurality of methods for updating operation flags are prepared for each instruction. As a result, a relatively large-scale hardware is necessary for the instruction decoder.
In addition, the operation flag register that is to be updated has to be designated for each instruction according to the conventional art. As a result, when instruction codes are assigned to instructions, the length of the field for designating the operation is increased, and consequently the code size is increased.